The present invention relates to electronic circuits, and more particularly, to techniques for multiplexing delayed signals.
FIG. 1 illustrates an example of a prior art integrated circuit (IC) 100. IC 100 includes several input driver circuits 101 and several input register circuit blocks 102. Input signals are driven from external sources outside IC 100 to core 103 through input driver circuits 101 and input register circuit blocks 102. IC 100 is a field programmable gate array, and core 103 includes numerous programmable logic circuits.
FIG. 2 illustrates prior art architectures of an input driver circuit 101 and an input register circuit block 102. Input driver circuit 101 includes an external terminal pad 231 and an input buffer circuit 232. Input register circuit block 102 includes delay circuit block 201, multiplexers 202-205, power saving decoder 206, register 208, configuration random access memory (CRAM) circuits 211-215, and decoders 221-224.
An input signal can be driven from an external source into IC 100 through pad 231 to an input of input buffer 232. Buffer 232 drives the input signal to delay circuit block 201 as signal D0. Delay circuit block 201 delays signal D0 to generate delayed signals. The delayed signals are delayed by 45°, 90°, 135°, 180°, 225°, 270°, and 315° relative to signal D0, where 360° equals one period of signal D0. Six delayed signals are routed to the 1-6 inputs of multiplexers 202-204. A seventh delayed signal is routed to the 7 input of multiplexer 203.
The output signal generated at the O output of multiplexer 203 is routed to the 1 input of multiplexer 205. A register scan input signal REGSCANIN is routed to the 0 input of multiplexer 205. REGSCANIN can be used as a test signal. Memory circuits 211-215 store configuration memory signals. A configuration memory signal stored in memory circuit 215 is routed to the 2 input of multiplexer 205.
The output signal generated at the O output of multiplexer 205 is routed to the D input of register 208. Register 208 transmits the logic state at its D input to its Q output in response to a rising edge in a clock signal CLK. The signal stored at the Q output of register 208 is routed to the 7 input of multiplexer 202 and to the 7 input of multiplexer 204. The signal stored at the Q output of register 208 is also routed out of block 102 as a register scan output test signal REGSCANOUT. The signal stored at the Q output of register 208 is set to a logic high state by signal PRE and set to a logic low state by signal CLR.
Decoders 221-224 decode the configuration memory signals stored in memory circuits 211-214, respectively, to generate decoded signals. Each of the decoders 221-223 decodes 3 configuration memory signals to generate 8 decoded signals. The decoded signals generated by decoders 221-223 are routed to the select inputs of multiplexers 202-204, respectively. Decoder 224 decodes 2 configuration memory signals stored in memory circuit 214 to generate 3 decoded signals that are routed to the select inputs of multiplexer 205. The configuration memory signals stored in memory circuits 211-214 determine which input signals multiplexers 202-205, respectively, transmit to their O outputs. The output signals DATAIN0 and DATAIN1 at the O outputs of multiplexers 202 and 204, respectively, are routed to core 103.
The 24 decoded output signals of decoders 221, 222, and 223 are also routed to the inputs of power saving decoder 206. Power saving decoder 206 decodes the 24 decoded output signals of decoders 221-223 to generate 6 control signals that are routed to delay circuit block 201. Each of the delay circuits in delay circuit block 201 has a variable delay. The 6 control signals generated by decoder 206 determine the delays of the delay circuits in delay circuit block 201. The delays of the delay circuits in block 201 can be varied to generate delays of 45°, 90°, 135°, 180°, 225°, 270°, and 315° in the delayed signals relative to signal D0 for input signals D0 having different frequencies. The delays of the delay circuits in block 201 vary in response to changes in the logic states of the 6 control signals generated by decoder 206.